Organic Open-Source Plugin + MCP EDA

Design chips with
natural language

From your first prompt toward DRC/LVS/STA sign-off-clean GDS — AI-driven at every step, with expert judgment where it counts. Lowers the barrier to chip design; it doesn't replace engineering judgment.

Get Started Design Rationale
60AI Skills
56MCP Tools
918Verification Programs
8ICs sign-off-validated

Open-sourcing 2026/7/20 · join in

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Leave your email to hear the moment vibe-IC goes open source. And if you'd like to take part in the project, tell us a little about yourself — we'd love to build it together.

Three-phase flow — Prompt to Chip

Every IC starts from a user-friendly dialogue and ends with a verified chip on FPGA.

No technical jargon — AI translates your product needs into silicon.

01

Spec — Any input → L1-L27 structured JSON

What users can understand

  • Any input — existing docs, a free-text prompt, or a plain-language dialogue with the IC-Expert Agent — converges to the same L1–L27 structured JSON, every decision traceable to source.
Deliverable: L1-L27 JSON + human_docs/L*.md
02

Design — L1-L27 → verified netlist + FPGA SOF

What engineers can understand

  • RTL → lint → CDC → sim → formal → synth → STA → DFT → LEC, plus the analog frontend — every step gated by deterministic programs, so the same input always yields the same output.
Acceptance: LEC PASS + FPGA on-board PASS
03

Silicon — netlist → GDS → tapeout → manufacturing

What the foundry needs

  • PnR → CTS → routing → multi-corner STA → IR/EM/antenna → DRC/LVS → GDSII → tapeout → fab, with the analog + mixed-signal backend tracks integrated.
Acceptance: tapeout_checklist 4/4 + flow_compliance --strict: PASS
See the full 63-step flow Quick install

MCP EDA Server

Model Context Protocol is the wire between Claude and the silicon stack. We open-sourced an MCP server that exposes 56 tools — synthesis, place & route, GDS export, FPGA programming, scope capture, protocol testing, SPICE corner sweep, analog layout, xschem netlist, ADC read, oracle dump — as one declarative interface.

01

Forked, bug-fixed EDA

vibeic-eda — the image it runs on

  • 21 tracked tool forks: OpenROAD, OpenSTA, Yosys+abc, ngspice, Magic, Netgen, iverilog, KLayout, Verilator, cocotb, cocotb-coverage, pyuvm, sby
  • 33 gatekeeper-verified FAIL→PASS fixes (+14 adopted-proven) — each with a reproducible proof vs the stock binary
  • e.g. OpenROAD post-route repair (289→0 slew where stock segfaults); netgen catches a silent LVS false-pass; yosys ripple→prefix lift
  • One pull, no per-tool forking: docker pull ghcr.io/vibeic/vibeic-eda:0.2.54, forks pinned by commit SHA
Fixed where stock OSS EDA breaks
02

56 tools, one interface

mcp-eda-server v1.0.0 — 56 tools

  • 48 EDA tools: lint, synth, sim, formal, PnR, GDS, STA, DFT, LVS, DRC, IR drop, FPGA compile, SPICE corner sweep, xschem netlist, analog layout, oracle dump, ...
  • 7 device tools: scope capture / periodic-pulse check, camera capture / LED-diff, FPGA program / detect / ADC read
  • Live MCP resources: scope://current_setup, fpga://board_status
  • Vendor-neutral MCP — works with Claude Code / Desktop / any MCP client
Open source, any one, any agent
03

Why it matters

Self-healing diagnostics + anti-fabrication

  • No silent PASS — every tool failure surfaces actionable hints
  • Auto-recover: docker-group self-heal, DRT-0073 PnR retry, layermap auto-discovery
  • Provenance logged: every call records {tool, version, input/output hash, exit, duration}
  • Pre-flight eda_doctor + post-build eda_pdk_lint catch broken setups before tapeout
Tools you can trust mid-tapeout
MCP architecture diagram Claude Code (agent / IDE) mcp-eda server v1.0.0 — 56 tools open source · MCP-native vibeic-eda forked · bug-fixed Yosys · OpenROAD KLayout · Magic · … JSON-RPC · tools[] structured results docker exec stdout + JSON auto-register src/devices/ scope · fpga drivers Drop a vendor manifest.json → new tool/resource appears with zero server-side code.

60 AI Skills

Each skill is a domain expert guiding one step of the IC design flow.

Phase 1 — Spec extraction (digital + analog A1, every input → DOC→JSON → L1-L27 JSON)

Digital: L1–L13 layer extractors + dialogue. Analog A1: per-block spec extraction.

phase1phase1-output-verifyphase1-completeness-deep-reviewphase1-coverage-loopspec-reviewspec-validatoranalog-spec-extractic-expert-agent
Phase 2 — Design (digital RTL + analog A2-A4 frontend → verified netlist + FPGA SOF)

Digital: spec-to-RTL → lint → CDC → sim → formal → synth → DFT → LEC. Analog A2-A4: topology select → SPICE netlist → corner sweep (PVT).

phase2-rtl-verifyrtl-reviewrtl-repairformal-verifyequivalence-checkregression-managecheckpoint-gateppa-predicthls-c2rtlarchitecture-explorefpga-hps-bridgefpga-signaltapfpga-led-probe-allocationhw-debug-loopprotocol-timeline-assertprotocol-turnaround-auditscope-pattern-attestationcompliance-gate-spot-checkcatalog-glue-authorcommunity-backlog-submitanalog-topology-selectanalog-sizinganalog-sizing-loopanalog-netlist-genams-sim
Phase 3 — Silicon (digital signoff + analog A5-A9 backend + Mixed-signal M1-M4)

Digital: synth → PnR → STA → DRC/LVS/IR/EM → GDS → tapeout. Analog A5-A9: layout → PV → post-layout resim → hardmacro → HIL. Mixed-signal M1-M4: A+D merge → power domain → AMS cosim → top-level PV.

synth-doctorsta-reviewhold-fixdrc-fixlvs-triageir-drop-triageeco-plantapeout-checklistatpg-name-harmonizeyield-diagnosticphase3-backend-verifyanalog-layoutanalog-extraction-resimanalog-hardmacro-genanalog-hw-testbench-genanalog-hw-measureanalog-hw-tuning-loopanalog-output-verifymixed-signal-cosim
Cross-phase orchestration + closed-loop

Closed-loop runners + field/core-agent loops that span all three phases.

analog-flow-orchestratefield-agent-loopcore-agent-loopregression-issue-fix

918 Deterministic Programs

Chip-AGNOSTIC verification gates. Each program prevents one class of bugs — encoded as code, not prompts. 17,545 tests enforce that every program stays chip-agnostic.

Verification stack: L1 compliance.yaml regex on agent text · L2 programs verify on-disk artefacts · L3 MCP execution proof + provenance hash match · L4 real-hardware pass attestation.

Phase 1 — L1-L27 extraction + completeness (~45)

Doc-extraction harvest + per-layer typed-field depth + cross-document consistency.

phase1_doc_one_shot_runnerphase1_doc_presence_checkphase1_consistency_checkphase1_doc_input_completeness_checkphase1_gate_contract_checkphase1_k5_quality_checkphase1_quality_parity_checkphase1_structured_field_substance_checkphase1_coverage_report_genl1_electrical_specs_typed_depth_checkl3_opcode_argument_constraints_checkl4_regmap_enumerated_values_typed_checkl8_clock_domains_typed_checkl9_rtl_pin_consistency_checkl9_submodule_conformance_checkl10_tb_conformance_checkl12_behavioral_sequences_steps_typed_checkl_doc_structured_field_count_checkdoc_consistency_no_unresolved_conflicts_checkextraction_coverage_checkextraction_evidence_schema_checkdoc_extractxlsx_extract
Phase 2 — RTL hygiene + Spec↔RTL coherence + Verification (~120)

Lint patterns · CDC/RDC · synth wrapper · SDC · LEC · ATPG · testbench coverage.

phase2_one_shot_runnerrtl_hygiene_lintfsm_error_invariantnba_addr_read_race_checkperiodic_timer_vs_rx_activity_checkcdc_crossing_checkcdc_async_input_checkreset_dependency_checkderived_clock_sdc_required_checksdc_syntax_checksynth_wrapper_checksynth_netlist_checkmodule_port_auditintegration_spec_auditconstants_validationassertion_property_checkfault_atpg_runverilator_coverage_measurefunctional_state_transition_coverage_checkrtl_unit_test_coverage_checkrtl_precheck_gatebit_level_full_stack_tb_checksv_compat_checktestbench_exists_checkinternal_vs_external_timing_checkcross_constant_invariant_checkquartus_map_auditfpga_qsf_lintfpga_on_board_attestation_checkfpga_async_input_synchronizer_check
Phase 3 — Backend signoff (~50)

PnR progression · per-corner STA · IR/EM/antenna/SI · DRC/LVS/ERC · GDS audit · tapeout & foundry handoff.

phase3_one_shot_runnerphase3_backend_stepdef_stage_progression_checksta_report_checkir_drop_report_checkem_report_checkdrc_report_checklvs_report_checkpower_report_checkgds_size_checkchip_gds_canonical_real_file_checktapeout_signoff_checkfoundry_signoff_plan_checkfoundry_handoff_package_checksignoff_auditopenroad_tcl_deprecation_checkyosys_hilomap_required_checkyosys_script_template_checkpdk_consistency_checkpdk_yosys_flatten_for_quartuspnr_via_stack_completeness_check
Analog A1-A9 + Mixed-signal M1-M4 (~30)

Per-block spec → SPICE → corners → layout → PV → resim → hardmacro → HIL. M1 A+D merge · M3 AMS cosim · M4 top-level PV.

analog_a1_spec_extract_checkanalog_a2_topology_select_checkanalog_a3_netlist_gen_checkanalog_a4_corner_sweep_checkanalog_a5_layout_checkanalog_a6_post_layout_resim_checkanalog_a7_hardmacro_gen_checkanalog_a8_hw_verify_checkanalog_block_coverage_checkanalog_block_pv_checkanalog_corner_sweep_checkanalog_digital_interface_checkanalog_flow_compliance_checkanalog_hardmacro_checkanalog_hil_convergence_log_checkanalog_hw_spice_correlation_checkanalog_netlist_pdk_checkanalog_oracle_compareanalog_per_block_pv_completeness_checkanalog_pre_vs_post_layout_checkanalog_real_corner_sweepanalog_artefact_substance_checkanalog_content_detected_must_emit_l5_checkmixed_signal_cosim_checkpdk_analog_completeness_check
Anti-fabrication doctrine + Provenance (~40)

No silent PASS · every output SHA256-hashed in provenance.jsonl · 14-phrase stub-marker panel · symlink-in-canonical forbid · audit-chain timing heuristic.

provenance_loggerprovenance_checkprovenance_output_hash_completeness_checkfresh_agent_provenance_checkfpga_program_chain_attest_checkfpga_on_board_attestation_checkfpga_verification_audithardware_pass_attestation_checkmcp_execution_verifygate_evidence_completeness_checkcanonical_path_symlink_forbid_checkrtl_bug_report_schema_checkwaivers_schema_checkwaiver_growth_checkwaiver_staleness_checkfpga_gate_level_attestation_checktop_level_outputs_in_canonical_checkreports_subfolder_taxonomy_checkmetadata_content_substance_check
Flow orchestration + Compliance verdict (~25)

55-entity flow YAML · one_shot_runners · stage gates · final compliance verdict · Layout P migration.

phase1_one_shot_runnerphase2_one_shot_runnerphase3_one_shot_runnerphase23_one_shot_runnervibe_ic_one_shot_runneranalog_one_shot_runnerflow_compliance_checkflow_stage_checkstage1_compliancestage2_compliancestage3_compliancestage4_compliancephase23_completion_self_audit_checkmigrate_to_layout_p_path_layout
Protocol / CRC / hardware bring-up (~40)

Half-duplex turnaround · CRC bit-order · pulse decoder · packet length · scope pattern · oracle bytewise dump.

crc_bitorder_checkcrc_compute_done_before_tx_start_checkcrc_completeness_checkcrc_engine_isolation_checkcrc_q_settle_cycle_after_last_feed_checkcrc_residual_checkcrc_seed_consistency_checkcrc_validation_presentcrc_vector_genhandshake_checktristate_bus_checktristate_self_rx_mask_checkpulse_decoder_edge_checkpacket_length_check_presentprotocol_gap_checkprotocol_ip_simulation_required_checkprotocol_delimiter_consistency_checkscope_periodic_pulse_checkbist_window_calculatortester_oracle_health_checkcmd_response_conformance_checkhw_vs_rtl_verdict_check
IP catalog + Community backlog (~10)

Validated open-source IP query / pull / GDS attribution · backlog sanitization.

ip_catalog_queryip_catalog_pullip_catalog_validateip_catalog_reproduce_pullip_catalog_upstream_auditgds_ip_attributionbacklog_sanitize_checkpractical_notes_specificity_check

Full program list (918 programs) at vibe-ic/programs/

Technology stack

Open-source tools, open PDKs, open AI — no vendor lock-in.

EDA Tools

vibeic-eda — forked IIC-OSIC-TOOLS + 21 tool forks, 33 FAIL→PASS fixes, one pull

Process Nodes

SKY130 + GF180MCU + IHP-SG13G2 + custom PDK · NanGate45 / ASAP7 (research-only, not tapeout-capable)

FPGA Target

Intel MAX 10 (DE10-Lite) + Quartus Prime Lite — RTL prototype before silicon

AI Engine

Claude Code + MCP Server v1.0.0 — 56 tools (48 EDA + 7 device + 1 health), custom PDK

Quality

17,545 tests · 918 programs · 8 ICs validated · anti-fabrication doctrine

Knowledge Base

PostgreSQL + pgvector — IC spec semantic search + IP catalog

Built with ATLAS

Vibe-IC is the reference implementation of a methodology

Vibe-IC didn't appear by hand — it was created with ATLAS: an AI-Native, Program-First methodology (AI-Native · Try · Learn · Automate · Skill-back). The agent tries, learns its way to end-to-end, then crystallizes what works into deterministic code and backs up the rest with Skills. ATLAS is the method; Vibe-IC is the product — the proof it works in a domain with zero tolerance for error.

Explore the ATLAS methodology ATLAS on GitHub

Open to Everyone

Open to everyone — plugin your device, your IP, your knowledge.

01

Plugin Your Device

FPGA boards, testers, scopes, lab equipment

Drop a manifest and your device becomes an MCP tool instantly — zero server code changes.

Any hardware vendor can join the ecosystem
02

Plugin Your IP

Reusable IP blocks for the community

Contribute verified, reusable IP blocks (I2C, SPI, UART, CRC, FIFO, arbiters…) that plugin users call directly.

IP providers can reach every Vibe-IC user
03

Plugin Your Knowledge

Community backlogs that evolve the plugin

Every bug your agent finds becomes an IC-agnostic backlog — a general gate for everyone, no vendor data, no secrets.

Every user makes the plugin smarter for everyone
Explore the Open Platform

Hardware Lab (optional)

Physical devices for FPGA bring-up and on-board verification. Not required for simulation or GDS tapeout flows.

FPGA Board — Terasic DE10-Lite
# 1. Install Quartus 23.1 Lite (free)
#    intel.com/Quartus → Lite Edition
# 2. USB-Blaster udev rule
sudo cp quartus/linux64/51-usbblaster.rules \
  /etc/udev/rules.d/ && sudo udevadm control --reload
# 3. Tell MCP server where Quartus lives
#    Edit .claude/.mcp.json → env:
"QUARTUS_ROOTDIR": "/path/to/quartus",
"PATH": "/path/to/quartus/bin:..."
# 4. Verify: restart claude, then run
#    eda_device_list → quartus_pgm: satisfied
Oscilloscope — Keysight InfiniiVision
# No driver needed (Linux USB TMC built-in)
# 1. Plug in scope via USB
# 2. Grant permission
sudo usermod -aG plugdev $USER
# 3. Verify: log out/in, then
lsusb | grep 2a8d
# 4. Restart claude → eda_device_list
#    → scope: plugdev satisfied

Want to ship your own device, IP, or partner plugin? See the Open Platform page.