Organic Open-Source Plugin + MCP EDA · v1.6.606

Design chips with
natural language

From your first prompt to production-ready GDS — fully AI-driven. No IC design experience required.

Get Started View Source
56AI Skills
55MCP Tools
413Verification Programs
13ICs Validated

Three-phase flow — Prompt to Chip

Every IC starts from a user-friendly dialogue and ends with a verified chip on FPGA.

No technical jargon — AI translates your product needs into silicon.

01

Spec — Any input → L1-L13 structured JSON

What users can understand

  • Path A (existing docs): input/docs/ → 17 doc-extraction skills → phase1/input_doc/
  • Path B (natural language): PM Agent ↔ user dialogue → fact-graph → phase1/input_prompt/
  • Both paths converge: produce the same universal handoff phase1/generated_docs/L1..L13.json
  • Every decision traceable to source — extraction_evidence with line + paragraph anchors
Deliverable: L1-L13 JSON + human_docs/L*.md
02

Design — L1-L13 → verified netlist + FPGA SOF

What engineers can understand

  • Stage 1 (Steps 1-6): spec-to-RTL → lint → CDC/RDC → simulation → formal → FPGA early prototype
  • Stage 2 (Steps 7-13): SDC + synth → pre-layout STA → DFT scan + ATPG → post-DFT opt → LEC
  • Analog A2-A4 frontend: topology selection → SPICE netlist → corner sweep
  • 413 deterministic programs + 9 972 pytest cases ensure reproducible results
Acceptance: LEC PASS + FPGA on-board PASS
03

Silicon — netlist → GDS → tapeout → manufacturing

What the foundry needs

  • Stage 3 (Steps 14-30): pre-PnR Yosys → floorplan → CTS → routing → SPEF → multi-corner STA → IR/EM/antenna/SI → post-layout sim+SPICE → DRC/LVS/ERC → ECO
  • Stage 4 (Steps 31-36): power → metal fill → tapeout checklist → GDSII → foundry handoff → FPGA final sign-off
  • Stage 5 (Steps 37-40): fab → wafer sort → packaging → final ATE
  • Analog A5-A9 + mixed-signal M1-M4 backend tracks integrated under phase3/analog/ + phase3/mixed_signal/
Acceptance: tapeout_checklist 4/4 + flow_compliance --strict: PASS

Dual Organic Growth — Standing on Giants

An organic plugin built on the world's strongest AI. General skills grow as the AI giant grows. Domain expertise deepens through community contributions.

01

The AI Giant Grows

General skills — automatic

  • Built on the world's most capable AI (Claude) — not our own model
  • As the AI improves reasoning, coding, hardware knowledge — all 50 unified skills automatically produce better results
  • Zero effort from us — the platform lifts everything
We ride the giant. As it grows, we grow.
02

The Opensource Community Deepens

Domain expertise — community-driven

  • Every agent using the plugin can contribute back — when a bug is found, the agent asks: "What general gate would catch this class?"
  • 413 deterministic programs accumulate from real-world experience — each one prevents an entire class of bugs
  • IC design domain expertise that the AI alone doesn't have — encoded as code, not prompts
The plugin gets more professional with every contribution.

Open to Everyone

Open to everyone — plugin your device, your IP, your knowledge.

01

Plugin Your Device

FPGA boards, testers, scopes, lab equipment

  • Drop a manifest.json in src/devices/ — your device becomes an MCP tool instantly
  • FPGA boards, protocol testers, oscilloscopes, logic analyzers
  • Zero server code changes — the MCP server auto-registers new devices
Any hardware vendor can join the ecosystem
02

Plugin Your IP

Reusable IP blocks for the community

  • Contribute verified, reusable IP blocks (I2C slave, SPI master, UART, CRC engines, FIFO, arbiters...)
  • Extract small, independent IP from open-source ICs into the community database
  • Plugin users call these IPs directly — no need to regenerate common building blocks
IP providers can reach every Vibe-IC user
03

Plugin Your Knowledge

Community backlogs that evolve the plugin

  • When your agent finds a bug, it reviews the plugin: "What general gate would have caught this?"
  • Enhancement opportunities (not bugs) are recorded as IC-agnostic backlogs — no vendor data, no secrets
  • EDA tool vendors, foundries, design houses — anyone with IC design knowledge can contribute
Every user makes the plugin smarter for everyone

MCP EDA Server

Model Context Protocol is the wire between Claude and the silicon stack. We open-sourced an MCP server that exposes 55 tools — synthesis, place & route, GDS export, FPGA programming, scope capture, protocol testing, SPICE corner sweep, analog layout, xschem netlist, ADC read, oracle dump — as one declarative interface.

01

What is MCP?

A protocol, not a framework

  • Model Context Protocol — open standard from Anthropic, JSON-RPC over stdio
  • Three primitives: tools (do something), resources (read state), prompts (templates)
  • Vendor-neutral — works with Claude Code, Claude Desktop, any MCP client
  • Decouples agent reasoning from tool execution
One protocol, any model, any tool
02

What we built

mcp-eda-server v0.115.0 — 55 tools

  • 43 EDA tools: lint, synth, sim, formal, PnR, GDS, STA, DFT, LVS, DRC, IR drop, FPGA compile, SPICE corner sweep, xschem netlist, analog layout, oracle dump, ...
  • 12 device tools: scope capture/measure, FPGA program/detect/ADC read, MD-905 USB-HID tester, ID-bus opcode injector, camera LED diff
  • Live MCP resources: scope://current_setup, fpga://board_status
  • Wraps IIC-OSIC-TOOLS Docker — open-source EDA in one image
Open source, any one, any agent
03

Why it matters

Self-healing diagnostics + anti-fabrication

  • No silent PASS — every tool failure surfaces actionable hints
  • Auto-recover: docker-group self-heal, DRT-0073 PnR retry, layermap auto-discovery
  • Provenance logged: every call records {tool, version, input/output hash, exit, duration}
  • Pre-flight eda_doctor + post-build eda_pdk_lint catch broken setups before tapeout
Tools you can trust mid-tapeout
MCP architecture diagram Claude Code (agent / IDE) mcp-eda server v0.115.0 — 55 tools open source · MCP-native IIC-OSIC-TOOLS Yosys · OpenROAD KLayout · Magic JSON-RPC · tools[] structured results docker exec stdout + JSON auto-register src/devices/ scope · fpga · tester drivers Drop a vendor manifest.json → new tool/resource appears with zero server-side code.

56 AI Skills

Each skill is a domain expert guiding one step of the IC design flow.

Phase 1 — Spec extraction (digital + analog A1, both entries → L1-L13 JSON)

Digital: 17 doc-gen skills + dialogue. Analog A1: per-block spec extraction.

phase1phase1-output-verifyphase1-completeness-deep-reviewphase1-coverage-loopspec-reviewspec-validatoranalog-spec-extractpm-agentic-expert-agent
Phase 2 — Design (digital RTL + analog A2-A4 frontend → verified netlist + FPGA SOF)

Digital: spec-to-RTL → lint → CDC → sim → formal → synth → DFT → LEC. Analog A2-A4: topology select → SPICE netlist → corner sweep (PVT).

phase2-rtl-verifyrtl-reviewrtl-repairformal-verifyequivalence-checkregression-managecheckpoint-gateppa-predicthls-c2rtlarchitecture-explorefpga-hps-bridgefpga-signaltapfpga-led-probe-allocationhw-debug-loopprotocol-timeline-assertprotocol-turnaround-auditscope-pattern-attestationcompliance-gate-spot-checkcatalog-glue-authorcommunity-backlog-submitanalog-topology-selectanalog-sizinganalog-sizing-loopanalog-netlist-genams-sim
Phase 3 — Silicon (digital signoff + analog A5-A9 backend + Mixed-signal M1-M4)

Digital: synth → PnR → STA → DRC/LVS/IR/EM → GDS → tapeout. Analog A5-A9: layout → PV → post-layout resim → hardmacro → HIL. Mixed-signal M1-M4: A+D merge → power domain → AMS cosim → top-level PV.

synth-doctorsta-reviewhold-fixdrc-fixlvs-triageir-drop-triageeco-plantapeout-checklistatpg-name-harmonizeyield-diagnosticphase3-backend-verifyanalog-layoutanalog-extraction-resimanalog-hardmacro-genanalog-hw-testbench-genanalog-hw-measureanalog-hw-tuning-loopanalog-output-verifymixed-signal-cosim
Cross-phase orchestration + closed-loop

Closed-loop runners + field/core-agent loops that span all three phases.

analog-flow-orchestratefield-agent-loopcore-agent-loopregression-issue-fix

413 Deterministic Programs

Chip-AGNOSTIC verification gates. Each program prevents one class of bugs — encoded as code, not prompts. 9 972 pytest cases enforce that every program stays chip-agnostic.

Verification stack: L1 compliance.yaml regex on agent text · L2 programs verify on-disk artefacts · L3 MCP execution proof + provenance hash match · L4 real-hardware pass attestation.

Phase 1 — L1-L13 extraction + completeness (~45)

Doc-extraction harvest + per-layer typed-field depth + cross-document consistency.

phase1_doc_one_shot_runnerphase1_doc_presence_checkphase1_consistency_checkphase1_doc_input_completeness_checkphase1_gate_contract_checkphase1_k5_quality_checkphase1_quality_parity_checkphase1_structured_field_substance_checkphase1_coverage_report_genl1_electrical_specs_typed_depth_checkl3_opcode_argument_constraints_checkl4_regmap_enumerated_values_typed_checkl8_clock_domains_typed_checkl9_rtl_pin_consistency_checkl9_submodule_conformance_checkl10_tb_conformance_checkl12_behavioral_sequences_steps_typed_checkl_doc_structured_field_count_checkdoc_consistency_no_unresolved_conflicts_checkextraction_coverage_checkextraction_evidence_schema_checkdoc_extractxlsx_extract
Phase 2 — RTL hygiene + Spec↔RTL coherence + Verification (~120)

Lint patterns · CDC/RDC · synth wrapper · SDC · LEC · ATPG · testbench coverage.

phase2_one_shot_runnerrtl_hygiene_lintfsm_error_invariantnba_addr_read_race_checkperiodic_timer_vs_rx_activity_checkcdc_crossing_checkcdc_async_input_checkreset_dependency_checkderived_clock_sdc_required_checksdc_syntax_checksynth_wrapper_checksynth_netlist_checkmodule_port_auditintegration_spec_auditconstants_validationassertion_property_checkfault_atpg_runverilator_coverage_measurefunctional_state_transition_coverage_checkrtl_unit_test_coverage_checkrtl_precheck_gatebit_level_full_stack_tb_checksv_compat_checktestbench_exists_checkinternal_vs_external_timing_checkcross_constant_invariant_checkquartus_map_auditfpga_qsf_lintfpga_on_board_attestation_checkfpga_async_input_synchronizer_check
Phase 3 — Backend signoff (~50)

PnR progression · per-corner STA · IR/EM/antenna/SI · DRC/LVS/ERC · GDS audit · tapeout & foundry handoff.

phase3_one_shot_runnerphase3_backend_stepdef_stage_progression_checksta_report_checkir_drop_report_checkem_report_checkdrc_report_checklvs_report_checkpower_report_checkgds_size_checkchip_gds_canonical_real_file_checktapeout_signoff_checkfoundry_signoff_plan_checkfoundry_handoff_package_checksignoff_auditopenroad_tcl_deprecation_checkyosys_hilomap_required_checkyosys_script_template_checkpdk_consistency_checkpdk_yosys_flatten_for_quartuspnr_via_stack_completeness_check
Analog A1-A9 + Mixed-signal M1-M4 (~30)

Per-block spec → SPICE → corners → layout → PV → resim → hardmacro → HIL. M1 A+D merge · M3 AMS cosim · M4 top-level PV.

analog_a1_spec_extract_checkanalog_a2_topology_select_checkanalog_a3_netlist_gen_checkanalog_a4_corner_sweep_checkanalog_a5_layout_checkanalog_a6_post_layout_resim_checkanalog_a7_hardmacro_gen_checkanalog_a8_hw_verify_checkanalog_block_coverage_checkanalog_block_pv_checkanalog_corner_sweep_checkanalog_digital_interface_checkanalog_flow_compliance_checkanalog_hardmacro_checkanalog_hil_convergence_log_checkanalog_hw_spice_correlation_checkanalog_netlist_pdk_checkanalog_oracle_compareanalog_per_block_pv_completeness_checkanalog_pre_vs_post_layout_checkanalog_real_corner_sweepanalog_artefact_substance_checkanalog_content_detected_must_emit_l5_checkmixed_signal_cosim_checkpdk_analog_completeness_check
Anti-fabrication doctrine + Provenance (~40)

No silent PASS · every output SHA256-hashed in provenance.jsonl · 14-phrase stub-marker panel · symlink-in-canonical forbid · audit-chain timing heuristic.

provenance_loggerprovenance_checkprovenance_output_hash_completeness_checkfresh_agent_provenance_checkfpga_program_chain_attest_checkfpga_on_board_attestation_checkfpga_verification_audithardware_pass_attestation_checkmcp_execution_verifygate_evidence_completeness_checkcanonical_path_symlink_forbid_checkrtl_bug_report_schema_checkwaivers_schema_checkwaiver_growth_checkwaiver_staleness_checkfpga_gate_level_attestation_checktop_level_outputs_in_canonical_checkreports_subfolder_taxonomy_checkmetadata_content_substance_check
Flow orchestration + Compliance verdict (~25)

55-entity flow YAML · one_shot_runners · stage gates · final compliance verdict · Layout P migration.

phase1_one_shot_runnerphase2_one_shot_runnerphase3_one_shot_runnerphase23_one_shot_runnervibe_ic_one_shot_runneranalog_one_shot_runnerflow_compliance_checkflow_stage_checkstage1_compliancestage2_compliancestage3_compliancestage4_compliancephase23_completion_self_audit_checkmigrate_to_layout_p_path_layout
Protocol / CRC / hardware bring-up (~40)

Half-duplex turnaround · CRC bit-order · pulse decoder · packet length · scope pattern · oracle bytewise dump.

crc_bitorder_checkcrc_compute_done_before_tx_start_checkcrc_completeness_checkcrc_engine_isolation_checkcrc_q_settle_cycle_after_last_feed_checkcrc_residual_checkcrc_seed_consistency_checkcrc_validation_presentcrc_vector_genhandshake_checktristate_bus_checktristate_self_rx_mask_checkpulse_decoder_edge_checkpacket_length_check_presentprotocol_gap_checkprotocol_ip_simulation_required_checkprotocol_delimiter_consistency_checkscope_periodic_pulse_checkbist_window_calculatortester_oracle_health_checkcmd_response_conformance_checkhw_vs_rtl_verdict_check
IP catalog + Community backlog (~10)

Validated open-source IP query / pull / GDS attribution · backlog sanitization.

ip_catalog_queryip_catalog_pullip_catalog_validateip_catalog_reproduce_pullip_catalog_upstream_auditgds_ip_attributionbacklog_sanitize_checkpractical_notes_specificity_check

Full program list (413 .py files) at vibe-ic/programs/

Technology stack

Open-source tools, open PDKs, open AI — no vendor lock-in.

EDA Tools

Powered by IIC-OSIC-TOOLS — 43 MCP EDA tools in one Docker image

Process Nodes

SKY130 + GF180MCU + IHP-SG13G2 + custom PDK

FPGA Target

Intel MAX 10 (DE10-Lite) + Quartus Prime Lite — RTL prototype before silicon

AI Engine

Claude Code + MCP Server v0.115.0 — 55 tools (43 EDA + 12 device), custom PDK

Quality

9 972 tests · 413 programs · 13 ICs validated · anti-fabrication doctrine

Knowledge Base

PostgreSQL + pgvector — IC spec semantic search + IP catalog

Validated end-to-end on 13 real ICs

Across 5 design classes — cryptographic primitive, secure processor, RISCV CPU (Verilog / SystemVerilog / VHDL / SpinalHDL), RISCV SoC, mixed-signal ΔΣ-ADC. Every step runs real open-source signoff inside the IIC-OSIC-TOOLS container — yosys + OpenROAD + klayout + magic + netgen + ngspice + iverilog+SDF + SymbiYosys.

Crypto / Secure-proc

SHA-256 ×3 variants · SPM

RISCV CPU

PicoRV32 · CV32E40P · Ibex · SERV

RISCV SoC

Subservient (SERV-SoC) · NEORV32 (VHDL via GHDL)

Mixed-signal

U-Hawaii ΔΣ-ADC — A1-A9 + M1-M4 tracks exercised on real ngspice/klayout artefacts

Documented edge cases

DarkRISCV (BRAM-as-flops over-utilisation) · VexRiscv (SpinalHDL out of scope)

First formal-verification PASS

SERV via SymbiYosys + RVFI BMC depth=10 on the real RTL

Why Vibe-IC?

Lower the barrier from decades of training to a conversation.

Traditional IC Design

  • 10+ years experience required
  • $1M+ commercial EDA tools
  • NDA-locked PDK
  • 6–12 months design cycle
  • $100K+ per tapeout
vs

Vibe-IC

  • Anyone — natural language
  • Open-source EDA — 43 tools in one Docker
  • Open + Custom PDK — SKY130, GF180, IHP-SG13G2 + any commercial PDK
  • 2–3 months incl. tapeout
  • $10K (Efabless chipIgnite)

Quick install

Four steps. The Docker image (~22 GB) bundles every EDA tool. Hardware lab is optional — simulation and GDS tapeout flows do not need physical devices.

01
Pull EDA Docker + run container
docker pull hpretl/iic-osic-tools:latest

docker run -d --name iic-eda \
  -v $HOME/designs:/design \
  hpretl/iic-osic-tools:latest --wait

--wait keeps the container alive so MCP can docker exec into it.

02
Clone + register MCP EDA server
git clone https://github.com/reyerchu/\
  AI_IC_design.git
cd AI_IC_design/mcp-eda-server
npm install

claude mcp add eda-tools \
  node $(pwd)/src/index.js \
  -e EDA_CONTAINER=iic-eda

Verify with claude mcp list — eda-tools should be listed.

03
Add marketplace + install vibe-ic plugin
# start an interactive Claude session
claude

# inside the session, run two slash commands:
> /plugin marketplace add \
    /path/to/AI_IC_design/vibe-ic-marketplace

> /plugin install vibe-ic@vibe-ic-marketplace

/plugin commands run inside Claude Code — not in your shell.

04
Start designing
claude "Design a temperature sensor IC
        with I2C interface, 12-bit,
        alert output, SOIC-8 package"

Or invoke directly: /vibe-ic-all

Need full troubleshooting? See mcp-eda-server/INSTALL_GUIDE.md for prerequisites, Docker / Node / Quartus setup, and step-by-step verification.

Hardware Lab (optional)

Physical devices for FPGA bring-up and on-board verification. Not required for simulation or GDS tapeout flows.

FPGA Board — Terasic DE10-Lite
# 1. Install Quartus 23.1 Lite (free)
#    intel.com/Quartus → Lite Edition
# 2. USB-Blaster udev rule
sudo cp quartus/linux64/51-usbblaster.rules \
  /etc/udev/rules.d/ && sudo udevadm control --reload
# 3. Tell MCP server where Quartus lives
#    Edit .claude/.mcp.json → env:
"QUARTUS_ROOTDIR": "/path/to/quartus",
"PATH": "/path/to/quartus/bin:..."
# 4. Verify: restart claude, then run
#    eda_device_list → quartus_pgm: satisfied
Oscilloscope — Keysight InfiniiVision
# No driver needed (Linux USB TMC built-in)
# 1. Plug in scope via USB
# 2. Grant permission
sudo usermod -aG plugdev $USER
# 3. Verify: log out/in, then
lsusb | grep 2a8d
# 4. Restart claude → eda_device_list
#    → scope: plugdev satisfied

Want to ship your own device, IP, or partner plugin? See the Open Platform page.